高速折疊插值ADC采樣時間失配誤差校準電路設計
發(fā)布時間：2019-05-24 18:10
【摘要】：折疊插值ADC (Analog-to-Digital Converter,模數(shù)轉換器)相比于全并行結構ADC在獲得高速度的同時也減小了芯片的面積和功耗,在高速ADC中得到了廣泛的應用。但現(xiàn)如今單片ADC很難達到很高采樣速率的要求,因此時間交織結構ADC越來越多的被采用,然而各子ADC之間存在各種誤差,會對ADC的性能造成很大影響,其中各通道間的采樣時序誤差是最關鍵也最難校準的一個環(huán)節(jié),成為該領域研究的熱點。本文對時間交織ADC通道間失配誤差校準技術的研究現(xiàn)狀做了詳細的調研,針對8位,單通道采樣頻率500MHz的四通道折疊插值時間交織ADC,分析了各子通道間誤差對ADC輸出結果的影響,并通過理論分析以及行為級建模論證了設計采樣時間失配誤差校準電路的必要性,得出本文所述時間交織ADC各通道間的采樣時序偏差應小于2.5ps。研究典型的采樣時間失配誤差校準技術,在此基礎上確定了采用全差分模擬校準環(huán)路,將采樣時序偏差轉化為占空比信息進行校準的校準電路,包括整形電路、邊沿檢測電路、全差分連續(xù)時間積分器、跨導放大器等。其中邊沿檢測電路將采樣時序偏差轉化為占空比信息,且在電路中引入了手動調整模塊,通過改變電路中流過的電流大小細微的調整檢測到的占空比信息,能夠進行后臺調整;積分器電路中根據(jù)增益、擺幅等確定積分器中運放架構的選擇和設計,積分器RC常數(shù)的確定等;跨導放大器中通過負反饋提高電路的線性度,得到了非常線性的跨導增益。最后對整個校準環(huán)路的校準效果進行了仿真驗證。本文基于TSMC 0.18μmCMOS工藝,在2V電源電壓下,利用Cadence Spectre軟件對設計的校準電路進行仿真,仿真結果表明,對于1GHz的差分輸入時鐘信號,四通道采樣時鐘為其不同相位的二分頻信號,當延遲其中一路100ps時,校準環(huán)路能自動將輸出信號的采樣時間間隔校準至500.308ps,當進一步改變手動控制字時,采樣時間間隔被校準至499.992ps,滿足了 8位四通道時間交織ADC對采樣時序誤差的要求。
[Abstract]:Compared with the full parallel architecture ADC, folding interpolation ADC (Analog-to-Digital Converter, Analog-to-Digital Converter) not only obtains high speed, but also reduces the area and power consumption of the chip, and has been widely used in high-speed ADC. However, nowadays, single-chip ADC is difficult to meet the requirements of high sampling rate, so the time interleaving structure ADC is more and more adopted. However, there are all kinds of errors between the sub-ADC, which will have a great impact on the performance of ADC. Among them, the sampling timing error between channels is the most critical and difficult to calibrate, which has become the focus of research in this field. In this paper, the research status of mismatch error calibration technology between time interleaving ADC channels is investigated in detail. For 8 bits, single channel sampling frequency 500MHz, four channel folding interpolation time interleaving ADC, The influence of errors between subchannels on the output results of ADC is analyzed, and the necessity of designing sampling time mismatch error calibration circuit is demonstrated by theoretical analysis and behavior level modeling. It is concluded that the sampling time series deviation between the channels of the time interleaving ADC described in this paper should be less than 2.5 PS. The typical calibration technology of sampling time mismatch error is studied. on this basis, the calibration circuit which uses full difference analog calibration loop to convert the sampling timing deviation into duty cycle information is determined, including shaping circuit and edge detection circuit. Full difference continuous time Integrator, transconductive amplifier, etc. The edge detection circuit converts the sampling timing deviation into duty cycle information, and introduces a manual adjustment module into the circuit. By changing the current size of the circuit, the detected duty cycle information can be adjusted in the background. In the Integrator circuit, the selection and design of the operational amplifier architecture and the determination of the RC constant of the Integrator are determined according to the gain and swing, and the very linear transconductivity gain is obtained by improving the linearity of the circuit by negative feedback in the transconductive amplifier. Finally, the calibration effect of the whole calibration loop is verified by simulation. In this paper, based on TSMC 0.18 渭 m CMOS process, the calibration circuit is simulated by Cadence Spectre software at 2V power supply voltage. The simulation results show that for the differential input clock signal of 1GHz, The four-channel sampling clock is its binary signal of different phases. when one of the 100ps is delayed, the calibration loop can automatically calibrate the sampling time interval of the output signal to 500.308ps. when the manual control word is further changed, the calibration loop can automatically calibrate the sampling time interval of the output signal to 500.308ps. when the manual control word is further changed, The sampling time interval is calibrated to 499.992ps, which meets the requirements of 8-bit four-channel time interleaving ADC for sampling timing error.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN792
本文編號：2485074
[Abstract]:Compared with the full parallel architecture ADC, folding interpolation ADC (Analog-to-Digital Converter, Analog-to-Digital Converter) not only obtains high speed, but also reduces the area and power consumption of the chip, and has been widely used in high-speed ADC. However, nowadays, single-chip ADC is difficult to meet the requirements of high sampling rate, so the time interleaving structure ADC is more and more adopted. However, there are all kinds of errors between the sub-ADC, which will have a great impact on the performance of ADC. Among them, the sampling timing error between channels is the most critical and difficult to calibrate, which has become the focus of research in this field. In this paper, the research status of mismatch error calibration technology between time interleaving ADC channels is investigated in detail. For 8 bits, single channel sampling frequency 500MHz, four channel folding interpolation time interleaving ADC, The influence of errors between subchannels on the output results of ADC is analyzed, and the necessity of designing sampling time mismatch error calibration circuit is demonstrated by theoretical analysis and behavior level modeling. It is concluded that the sampling time series deviation between the channels of the time interleaving ADC described in this paper should be less than 2.5 PS. The typical calibration technology of sampling time mismatch error is studied. on this basis, the calibration circuit which uses full difference analog calibration loop to convert the sampling timing deviation into duty cycle information is determined, including shaping circuit and edge detection circuit. Full difference continuous time Integrator, transconductive amplifier, etc. The edge detection circuit converts the sampling timing deviation into duty cycle information, and introduces a manual adjustment module into the circuit. By changing the current size of the circuit, the detected duty cycle information can be adjusted in the background. In the Integrator circuit, the selection and design of the operational amplifier architecture and the determination of the RC constant of the Integrator are determined according to the gain and swing, and the very linear transconductivity gain is obtained by improving the linearity of the circuit by negative feedback in the transconductive amplifier. Finally, the calibration effect of the whole calibration loop is verified by simulation. In this paper, based on TSMC 0.18 渭 m CMOS process, the calibration circuit is simulated by Cadence Spectre software at 2V power supply voltage. The simulation results show that for the differential input clock signal of 1GHz, The four-channel sampling clock is its binary signal of different phases. when one of the 100ps is delayed, the calibration loop can automatically calibrate the sampling time interval of the output signal to 500.308ps. when the manual control word is further changed, the calibration loop can automatically calibrate the sampling time interval of the output signal to 500.308ps. when the manual control word is further changed, The sampling time interval is calibrated to 499.992ps, which meets the requirements of 8-bit four-channel time interleaving ADC for sampling timing error.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN792
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